AMD

The AMD Opteron™ 2300/8300 series is the third generation of AMD’s Opteron™ micro-processor, codenamed Shanghai.  Shanghai is the evolutionary successor to the second generation Barcelona architecture, combining a die shrink of 45nm with its quad-core architecture supporting 2P, 4P and 8P per core.

Shanghai achieves this 45nm die shrink using a new Immersion Lithography process.  This allows for a lower operating voltage, which directly decreases power consumption and the amount of heat generated.  Shanghai also introduces a larger L3 cache, increasing the cache size from 2MB to 6MB.  This alone is expected to boost performance by up to 5-10%.  Additionally, Shanghai has upgraded the on board memory controller to be able to handle faster memory.  This new memory controller is now capable of handling DDR2 800 MHz or PC2-6400 memory, increasing the processor's memory bandwidth from 10.6 GB/s to 12.8 GB/s.  Shanghai continues to utilize the AMD Direct Connect Architecture, which helps to eliminate bottlenecks by directly connecting CPU, memory, and I/O for reduced latency and optimized memory performance.  AMD Direct Connect Architecture results in the Shanghai line of processors realizing a high performance-per-watt ratio.

 

 At the heart of the AMD Opteron™ micro-processor is the HyperTransport™ interconnect.  AMD pioneered this revolutionary interface in 2003, and it has become an open standard technology managed, promoted, and licensed to the industry at large by the HyperTransport Consortium.  This third generation Shanghai micro-architecture updates the Opteron™ Family to HyperTransport™ 3.0, which increases bandwidth by up to 17.6 GB/s for a maximum of 25.6 GB/s.  HyperTransport™ technology is a high-speed, bi-directional, low latency, point-to-point communication link that provides a scalable bandwidth interconnect between computing cores, I/O subsystems, memory banks and other chipsets.  AMD Opteron™ processors support up to three coherent HyperTransport™ links, yielding up to 57.6 GB/s peak bandwidth per processor.

HyperTransport™ Technology is designed to:

• Provide significantly more bandwidth than current technologies
• Use low-latency responses and low pin counts
• Maintain compatibility with legacy PC buses while being extensible to new SNA (Systems Network Architecture) buses
• Appear transparent to operating systems and offer little impact on peripheral drivers

 

Enhanced AMD PowerNow! Technology with Independent Dynamic Core Technology:

• Allows processors and cores to operate at various voltages and frequencies, depending on usage and workload, which can reduce TCO and lower power consumption in the datacenter 
• Enables more granular power management capabilities to reduce processor energy consumption
• Memory controller power consumption can be reduced, by shutting down logic that is not being used, for further reductions in power consumption 

 Dual Dynamic Power Management™

• Enables more granular power management capabilities to reduce processor energy consumption
• Separate power planes for cores and memory controller, for optimum power consumption and performance, creating more opportunities for power savings within the cores and memory controller
  

 AMD CoolCore™ Technology

• Reduces processor energy consumption by turning off unused parts of the processor. For example, the memory controller can turn off the write logic when reading from memory, helping reduce system power
• Works automatically without the need for drivers or BIOS enablement
• Power can be switched on or off within a single clock cycle, saving energy with no impact to performance
  

 Integrated DDR2 DRAM Controller with AMD Memory Optimizer Technology

• 128-bit memory channel can be divided into two independent 64-bit memory channels for improving memory access efficiency
• Larger memory buffers for increased throughput
• Write bursting to minimize read/write transitions for greater throughput
• Optimized DRAM paging algorithm to intelligently predict and retrieve data needed from main memory for greater throughput
• Core prefetchers can pull data directly from L1 cache to decrease latency and to spare L2 bandwidth
  

 AMD Smart Fetch Technology

• Helps reduce power consumption by allowing idle cores to enter a "halt" state, causing them to draw even less power during processing idle times
• Data from the L1 and L2 cache are transferred to the L3 cache before the idle cores enter a "halt" state
• Contents of the idle cores can be intelligently retrieved from the shared L3 cache, so the idle cores can remain "halted"

 AMD Balanced Smart Cache

• Large shared L3 cache shares data between cores efficiently while helping reduce latency to main memory
• Dedicated L1 and L2 cache per core helps performance of virtualized environments and large databases by reducing cache pollution associated with a shared L2 cache
• The L1 cache of AMD Opteron processors can handle double the number of loads per cycle as Second-Generation AMD Opteron processors to help keep CPU cores busy

 AMD Wide Floating Point Accelerator

• 128-bit SSE floating-point capabilities enable each processor to simultaneously execute up to four flops per clock per core (up to four times the floating-point computations of previous AMD Opteron™ processors) for significantly improved performance in compute-intensive and workstation applications
• Instruction fetch bandwidth, data-cache bandwidth, and memory-controller-to-cache bandwidth have all been doubled over previous AMD Opteron processors to help keep the 128-bit floating-point pipeline full

 

 AMD Virtualization™ (AMD-V™) with Rapid Virtualization Indexing

• Designed to greatly increase performance of virtualized applications by allowing virtual machines to directly manage memory with less hypervisor intervention and associated overhead
• Improves the efficiency of switching between virtual machines, helping improve performance
• Effectively isolates virtual machines for secure operation

 

 

 AMD Istanbul and 6 core architecture

 

AMD is further extending its Opteron™ line by offering a new 6 core on-die processor code-named Istanbul.  Istanbul will extend the Opteron's performance by  offering 6 distinct on-die cores with support of up to 8 processors per core.  Istanbul also provides an even larger L3 cache, and a new HyperTransport™ Technology called HTAssist.  HT Assist greatly decreases traffic between multiple sockets, thereby improving memory bandwidth.  What may be even more appealing is that AMD Istanbul uses AMD's existing Socket F (1207) infrastructure, meaning that an upgrade to Istanbul on many platforms will only require a BIOS upgrade!  Stay tuned for more exciting news on AMD's Istanbul release.

 

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