KNIGHTS LANDING CLUSTERS
Solve Your Biggest Challenges Faster with a Knights Landing Cluster
The Knights landing, Intel Xeon Phi processor is a bootable host processor that delivers massive parallelism and vectorization to support the most demanding High Performance Computing (HPC) applications. The integrated and power-efficient architecture delivers significantly more compute per unit of energy consumed versus comparable platforms to give you an improved total cost of ownership. The integration of memory and fabric topples the memory wall and reduces cost to help you solve your biggest challenges faster. Read the MFDn Case Study.
Knights landing Cache Organization
2nd generation Intel Xeon Phi processors code-named Knights Landing (KNL) are specialized computing platforms capable of delivering better performance than general-purpose CPUs such as Intel Xeon products for some applications. Applications run best on Knights Landing if they have high degree of parallelism and well-behaved communication with memory. Read the BerkeleyGW Case Study.
Intel Xeon Phi Product Family
- Highly-parallel performance: Up to 72 cores with deep out-of-order buffers, Intel Advanced Vector Extensions 512 and 3x single-thread performance compared to the previous generation product
- Power-efficient architecture: Delivers significantly more compute per unit of energy consumed
- Simplified code modernization: Reduce programming efforts and downtime by sharing code and developer base with Intel Xeon processors
- Seamless IT manageability: Common x86 architecture delivers best utilization across any workload
- Future-ready code investment: Code is flexible, portable, and reusable into the future as it is optimized for a general-purpose architecture using open standards
In Knights Landing, each of its ≤ 72 cores has an L1 cache, pairs of cores are organized into tiles with a slice of the L2 cache symmetrically shared between the two cores, and the L2 caches are connected to each other with a mesh. All caches are kept coherent by the mesh with the MESIF (Modified Exclusive Shared Invalid Forward) protocol states of cache lines. In the mesh, each vertical and horizontal link is a bidirectional ring.
To maintain cache coherency, KNL has a distributed tag directory (DTD), organized as a set of per-tile tag directories (TDs), which identifies the state and the location on the chip of any cache line. For any memory address, the hardware can identify with a hash function the TD responsible for that address.
These improvements in cache organization in KNL come with increased complexity of the chip hardware. To manage this complexity and set the optimal mode of operation for any given computational application, the programmer has access to cache clustering modes.
Knights Landing Products
2nd generation Intel Xeon Phi processors code-named Knights Landing (KNL) provide up to 3X higher performance than the 1st generation, Knights Corner (KNC). With on-board high-bandwidth memory and optional integrated high-speed fabric—plus the availability of socket form-factor — these powerful components transform the fundamental building block of technical computing.